83 lines
3.2 KiB
C++
83 lines
3.2 KiB
C++
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#ifndef __STM32_TIMER_HPP
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#define __STM32_TIMER_HPP
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#include "stm32_system.h"
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#include <tim.h>
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#include <array>
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class Stm32Timer {
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public:
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/**
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* @brief Starts multiple timers deterministically and synchronously from the
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* specified offset.
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*
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* All timers are atomically (*) put into the following state (regardless of
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* their previous state/configuration):
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* - TIMx_CNT will be initialized according to the corresponding counter[i] parameter.
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* - If the timer is in center-aligned mode, it will be set to up-counting direction.
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* - The update repetition counter is reset to TIMx_RCR (if applicable).
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* - The prescaler counter is reset.
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* - Update interrupts are disabled.
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* - The counter put into running state.
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*
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* This function is implemented by generating an update event on all selected timers.
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* That means as a side effect all things that are connected to the update event
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* except the interrupt routine itself (i.e. ADCs, DMAs, slave timers, etc) will
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* be triggered.
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*
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* Also you probably want to disable any connected PWM outputs to prevent glitches.
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*
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* (*) Best-effort atomically. There will be skew of a handful of clock cycles
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* but it's always the same given the compiler version and configuration.
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*/
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template<size_t I>
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static void start_synchronously(std::array<TIM_HandleTypeDef*, I> timers, std::array<size_t, I> counters) {
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start_synchronously_impl(timers, counters, std::make_index_sequence<I>());
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}
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private:
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#pragma GCC push_options
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#pragma GCC optimize (3)
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template<size_t I, size_t ... Is>
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static void start_synchronously_impl(std::array<TIM_HandleTypeDef*, I> timers, std::array<size_t, I> counters, std::index_sequence<Is...>) {
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for (size_t i = 0; i < I; ++i) {
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TIM_HandleTypeDef* htim = timers[i];
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// Stop the timer so we can start all of them later more atomically.
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htim->Instance->CR1 &= ~TIM_CR1_CEN;
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// Generate update event to force all of the timer's registers into
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// a known state.
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__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
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htim->Instance->EGR |= TIM_EGR_UG;
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__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
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// Load counter with the desired value.
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htim->Instance->CNT = counters[i];
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}
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register volatile uint32_t* cr_addr[I];
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register uint32_t cr_val[I];
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for (size_t i = 0; i < I; ++i) {
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cr_addr[i] = &timers[i]->Instance->CR1;
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cr_val[i] = timers[i]->Instance->CR1 | TIM_CR1_CEN;
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}
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// Restart all timers as atomically as possible.
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// By inspection we find that this is compiled to the following code:
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// f7ff faa0 bl 800bdd0 <cpu_enter_critical()>
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// f8c9 6000 str.w r6, [r9]
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// f8c8 5000 str.w r5, [r8]
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// 603c str r4, [r7, #0]
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// f7ff fa9d bl 800bdd8 <cpu_exit_critical(unsigned long)>
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uint32_t mask = cpu_enter_critical();
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int dummy[I] = {(*cr_addr[Is] = cr_val[Is], 0)...};
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(void)dummy;
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cpu_exit_critical(mask);
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}
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#pragma GCC pop_options
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};
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#endif // __STM32_TIMER_HPP
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