417 lines
12 KiB
C
417 lines
12 KiB
C
/**
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******************************************************************************
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* @file stm32f4xx_it.c
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* @brief Interrupt Service Routines.
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******************************************************************************
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*
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* COPYRIGHT(c) 2018 STMicroelectronics
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_hal.h"
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#include "stm32f4xx.h"
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#include "stm32f4xx_it.h"
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#include "cmsis_os.h"
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#include <stdbool.h>
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/* USER CODE BEGIN 0 */
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#include <Drivers/STM32/stm32_system.h>
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/* USER CODE END 0 */
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/* External variables --------------------------------------------------------*/
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extern PCD_HandleTypeDef hpcd_USB_OTG_FS;
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extern ADC_HandleTypeDef hadc1;
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extern ADC_HandleTypeDef hadc2;
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extern ADC_HandleTypeDef hadc3;
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extern CAN_HandleTypeDef hcan1;
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extern DMA_HandleTypeDef hdma_spi3_tx;
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extern DMA_HandleTypeDef hdma_spi3_rx;
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extern SPI_HandleTypeDef hspi3;
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extern TIM_HandleTypeDef htim5;
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extern TIM_HandleTypeDef htim8;
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extern DMA_HandleTypeDef hdma_uart4_rx;
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extern DMA_HandleTypeDef hdma_uart4_tx;
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extern DMA_HandleTypeDef hdma_usart2_rx;
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extern DMA_HandleTypeDef hdma_usart2_tx;
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extern UART_HandleTypeDef huart4;
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extern UART_HandleTypeDef huart2;
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extern TIM_HandleTypeDef htim14;
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/******************************************************************************/
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/* Cortex-M4 Processor Interruption and Exception Handlers */
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/******************************************************************************/
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/**
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* @brief This function handles Non maskable interrupt.
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*/
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void NMI_Handler(void)
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{
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/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
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COUNT_IRQ(NonMaskableInt_IRQn);
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/* USER CODE END NonMaskableInt_IRQn 0 */
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/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
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/* USER CODE END NonMaskableInt_IRQn 1 */
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}
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__attribute__((used))
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void get_regs(void** stack_ptr) {
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TIM1->BDTR &= ~(TIM_BDTR_AOE_Msk | TIM_BDTR_MOE_Msk); // disable M0 PWM
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TIM8->BDTR &= ~(TIM_BDTR_AOE_Msk | TIM_BDTR_MOE_Msk); // disable M1 PWM
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void* volatile r0 __attribute__((unused)) = stack_ptr[0];
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void* volatile r1 __attribute__((unused)) = stack_ptr[1];
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void* volatile r2 __attribute__((unused)) = stack_ptr[2];
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void* volatile r3 __attribute__((unused)) = stack_ptr[3];
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void* volatile r12 __attribute__((unused)) = stack_ptr[4];
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void* volatile lr __attribute__((unused)) = stack_ptr[5]; // Link register
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void* volatile pc __attribute__((unused)) = stack_ptr[6]; // Program counter
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void* volatile psr __attribute__((unused)) = stack_ptr[7]; // Program status register
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void* volatile cfsr __attribute__((unused)) = (void*)SCB->CFSR; // Configurable fault status register
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void* volatile cpacr __attribute__((unused)) = (void*)SCB->CPACR;
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void* volatile fpccr __attribute__((unused)) = (void*)FPU->FPCCR;
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volatile bool preciserr __attribute__((unused)) = (uint32_t)cfsr & 0x200;
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volatile bool ibuserr __attribute__((unused)) = (uint32_t)cfsr & 0x100;
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volatile int stay_looping = 1;
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while(stay_looping);
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}
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/**
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* @brief This function handles Hard fault interrupt.
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*/
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__attribute__((naked))
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void HardFault_Handler(void)
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{
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__asm(
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" tst lr, #4 \n\t"
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" ite eq \n\t"
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" mrseq r0, msp \n\t"
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" mrsne r0, psp \n\t"
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" b get_regs \n\t"
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);
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}
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/**
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* @brief This function handles Memory management fault.
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*/
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void MemManage_Handler(void)
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{
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/* USER CODE BEGIN MemoryManagement_IRQn 0 */
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COUNT_IRQ(MemoryManagement_IRQn);
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/* USER CODE END MemoryManagement_IRQn 0 */
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while (1)
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{
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/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
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TIM1->BDTR &= ~(TIM_BDTR_AOE_Msk | TIM_BDTR_MOE_Msk); // disable M0 PWM
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TIM8->BDTR &= ~(TIM_BDTR_AOE_Msk | TIM_BDTR_MOE_Msk); // disable M1 PWM
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/* USER CODE END W1_MemoryManagement_IRQn 0 */
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}
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/* USER CODE BEGIN MemoryManagement_IRQn 1 */
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/* USER CODE END MemoryManagement_IRQn 1 */
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}
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/**
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* @brief This function handles Pre-fetch fault, memory access fault.
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*/
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void BusFault_Handler(void)
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{
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/* USER CODE BEGIN BusFault_IRQn 0 */
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COUNT_IRQ(BusFault_IRQn);
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/* USER CODE END BusFault_IRQn 0 */
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while (1)
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{
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/* USER CODE BEGIN W1_BusFault_IRQn 0 */
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TIM1->BDTR &= ~(TIM_BDTR_AOE_Msk | TIM_BDTR_MOE_Msk); // disable M0 PWM
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TIM8->BDTR &= ~(TIM_BDTR_AOE_Msk | TIM_BDTR_MOE_Msk); // disable M1 PWM
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/* USER CODE END W1_BusFault_IRQn 0 */
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}
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/* USER CODE BEGIN BusFault_IRQn 1 */
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/* USER CODE END BusFault_IRQn 1 */
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}
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/**
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* @brief This function handles Undefined instruction or illegal state.
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*/
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void UsageFault_Handler(void)
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{
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/* USER CODE BEGIN UsageFault_IRQn 0 */
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COUNT_IRQ(UsageFault_IRQn);
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/* USER CODE END UsageFault_IRQn 0 */
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while (1)
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{
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/* USER CODE BEGIN W1_UsageFault_IRQn 0 */
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TIM1->BDTR &= ~(TIM_BDTR_AOE_Msk | TIM_BDTR_MOE_Msk); // disable M0 PWM
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TIM8->BDTR &= ~(TIM_BDTR_AOE_Msk | TIM_BDTR_MOE_Msk); // disable M1 PWM
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/* USER CODE END W1_UsageFault_IRQn 0 */
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}
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/* USER CODE BEGIN UsageFault_IRQn 1 */
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/* USER CODE END UsageFault_IRQn 1 */
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}
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/**
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* @brief This function handles Debug monitor.
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*/
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void DebugMon_Handler(void)
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{
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/* USER CODE BEGIN DebugMonitor_IRQn 0 */
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COUNT_IRQ(DebugMonitor_IRQn);
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/* USER CODE END DebugMonitor_IRQn 0 */
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/* USER CODE BEGIN DebugMonitor_IRQn 1 */
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/* USER CODE END DebugMonitor_IRQn 1 */
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}
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/**
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* @brief This function handles System tick timer.
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*/
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void SysTick_Handler(void)
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{
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/* USER CODE BEGIN SysTick_IRQn 0 */
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COUNT_IRQ(SysTick_IRQn);
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/* USER CODE END SysTick_IRQn 0 */
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osSystickHandler();
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/* USER CODE BEGIN SysTick_IRQn 1 */
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/* USER CODE END SysTick_IRQn 1 */
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}
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/******************************************************************************/
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/* STM32F4xx Peripheral Interrupt Handlers */
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/* Add here the Interrupt Handlers for the used peripherals. */
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/* For the available peripheral interrupt handler names, */
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/* please refer to the startup file (startup_stm32f4xx.s). */
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/******************************************************************************/
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/**
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* @brief This function handles DMA1 stream0 global interrupt.
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*/
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void DMA1_Stream0_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA1_Stream0_IRQn 0 */
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COUNT_IRQ(DMA1_Stream0_IRQn);
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/* USER CODE END DMA1_Stream0_IRQn 0 */
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HAL_DMA_IRQHandler(&hdma_spi3_rx);
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/* USER CODE BEGIN DMA1_Stream0_IRQn 1 */
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/* USER CODE END DMA1_Stream0_IRQn 1 */
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}
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/**
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* @brief This function handles DMA1 stream2 global interrupt.
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*/
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void DMA1_Stream2_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA1_Stream2_IRQn 0 */
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COUNT_IRQ(DMA1_Stream2_IRQn);
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/* USER CODE END DMA1_Stream2_IRQn 0 */
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HAL_DMA_IRQHandler(&hdma_uart4_rx);
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/* USER CODE BEGIN DMA1_Stream2_IRQn 1 */
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/* USER CODE END DMA1_Stream2_IRQn 1 */
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}
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/**
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* @brief This function handles DMA1 stream4 global interrupt.
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*/
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void DMA1_Stream4_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA1_Stream4_IRQn 0 */
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COUNT_IRQ(DMA1_Stream4_IRQn);
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/* USER CODE END DMA1_Stream4_IRQn 0 */
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HAL_DMA_IRQHandler(&hdma_uart4_tx);
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/* USER CODE BEGIN DMA1_Stream4_IRQn 1 */
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/* USER CODE END DMA1_Stream4_IRQn 1 */
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}
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/**
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* @brief This function handles DMA1 stream5 global interrupt.
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*/
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void DMA1_Stream5_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA1_Stream5_IRQn 0 */
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COUNT_IRQ(DMA1_Stream5_IRQn);
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/* USER CODE END DMA1_Stream5_IRQn 0 */
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HAL_DMA_IRQHandler(&hdma_usart2_rx);
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/* USER CODE BEGIN DMA1_Stream5_IRQn 1 */
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/* USER CODE END DMA1_Stream5_IRQn 1 */
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}
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/**
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* @brief This function handles DMA1 stream6 global interrupt.
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*/
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void DMA1_Stream6_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA1_Stream6_IRQn 0 */
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COUNT_IRQ(DMA1_Stream6_IRQn);
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/* USER CODE END DMA1_Stream6_IRQn 0 */
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HAL_DMA_IRQHandler(&hdma_usart2_tx);
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/* USER CODE BEGIN DMA1_Stream6_IRQn 1 */
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/* USER CODE END DMA1_Stream6_IRQn 1 */
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}
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/**
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* @brief This function handles DMA1 stream7 global interrupt.
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*/
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void DMA1_Stream7_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA1_Stream7_IRQn 0 */
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COUNT_IRQ(DMA1_Stream7_IRQn);
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/* USER CODE END DMA1_Stream7_IRQn 0 */
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HAL_DMA_IRQHandler(&hdma_spi3_tx);
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/* USER CODE BEGIN DMA1_Stream7_IRQn 1 */
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/* USER CODE END DMA1_Stream7_IRQn 1 */
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}
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/**
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* @brief This function handles CAN1 TX interrupts.
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*/
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void CAN1_TX_IRQHandler(void)
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{
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/* USER CODE BEGIN CAN1_TX_IRQn 0 */
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COUNT_IRQ(CAN1_TX_IRQn);
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/* USER CODE END CAN1_TX_IRQn 0 */
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HAL_CAN_IRQHandler(&hcan1);
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/* USER CODE BEGIN CAN1_TX_IRQn 1 */
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/* USER CODE END CAN1_TX_IRQn 1 */
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}
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/**
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* @brief This function handles CAN1 RX0 interrupts.
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*/
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void CAN1_RX0_IRQHandler(void)
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{
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/* USER CODE BEGIN CAN1_RX0_IRQn 0 */
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COUNT_IRQ(CAN1_RX0_IRQn);
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/* USER CODE END CAN1_RX0_IRQn 0 */
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HAL_CAN_IRQHandler(&hcan1);
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/* USER CODE BEGIN CAN1_RX0_IRQn 1 */
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/* USER CODE END CAN1_RX0_IRQn 1 */
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}
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/**
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* @brief This function handles CAN1 RX1 interrupt.
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*/
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void CAN1_RX1_IRQHandler(void)
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{
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/* USER CODE BEGIN CAN1_RX1_IRQn 0 */
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COUNT_IRQ(CAN1_RX1_IRQn);
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/* USER CODE END CAN1_RX1_IRQn 0 */
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HAL_CAN_IRQHandler(&hcan1);
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/* USER CODE BEGIN CAN1_RX1_IRQn 1 */
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/* USER CODE END CAN1_RX1_IRQn 1 */
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}
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/**
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* @brief This function handles CAN1 SCE interrupt.
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*/
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void CAN1_SCE_IRQHandler(void)
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{
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/* USER CODE BEGIN CAN1_SCE_IRQn 0 */
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COUNT_IRQ(CAN1_SCE_IRQn);
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/* USER CODE END CAN1_SCE_IRQn 0 */
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HAL_CAN_IRQHandler(&hcan1);
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/* USER CODE BEGIN CAN1_SCE_IRQn 1 */
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/* USER CODE END CAN1_SCE_IRQn 1 */
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}
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/**
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* @brief This function handles USART2 global interrupt.
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*/
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void USART2_IRQHandler(void)
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{
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/* USER CODE BEGIN USART2_IRQn 0 */
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/* USER CODE END USART2_IRQn 0 */
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HAL_UART_IRQHandler(&huart2);
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/* USER CODE BEGIN USART2_IRQn 1 */
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/* USER CODE END USART2_IRQn 1 */
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}
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/**
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* @brief This function handles TIM8 trigger and commutation interrupts and TIM14 global interrupt.
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*/
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void TIM8_TRG_COM_TIM14_IRQHandler(void)
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{
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/* USER CODE BEGIN TIM8_TRG_COM_TIM14_IRQn 0 */
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COUNT_IRQ(TIM8_TRG_COM_TIM14_IRQn);
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/* USER CODE END TIM8_TRG_COM_TIM14_IRQn 0 */
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HAL_TIM_IRQHandler(&htim8);
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HAL_TIM_IRQHandler(&htim14);
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/* USER CODE BEGIN TIM8_TRG_COM_TIM14_IRQn 1 */
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/* USER CODE END TIM8_TRG_COM_TIM14_IRQn 1 */
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}
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/**
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* @brief This function handles SPI3 global interrupt.
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*/
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void SPI3_IRQHandler(void)
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{
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/* USER CODE BEGIN SPI3_IRQn 0 */
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COUNT_IRQ(SPI3_IRQn);
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/* USER CODE END SPI3_IRQn 0 */
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HAL_SPI_IRQHandler(&hspi3);
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/* USER CODE BEGIN SPI3_IRQn 1 */
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/* USER CODE END SPI3_IRQn 1 */
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}
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/**
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* @brief This function handles UART4 global interrupt.
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*/
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void UART4_IRQHandler(void)
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{
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/* USER CODE BEGIN UART4_IRQn 0 */
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COUNT_IRQ(UART4_IRQn);
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/* USER CODE END UART4_IRQn 0 */
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HAL_UART_IRQHandler(&huart4);
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/* USER CODE BEGIN UART4_IRQn 1 */
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/* USER CODE END UART4_IRQn 1 */
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}
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/* USER CODE BEGIN 1 */
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/* USER CODE END 1 */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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