322 lines
8.9 KiB
C
322 lines
8.9 KiB
C
|
/**
|
||
|
|
******************************************************************************
|
||
|
|
* File Name : TIM.c
|
||
|
|
* Description : This file provides code for the configuration
|
||
|
|
* of the TIM instances.
|
||
|
|
******************************************************************************
|
||
|
|
* @attention
|
||
|
|
*
|
||
|
|
* <h2><center>© Copyright (c) 2021 STMicroelectronics.
|
||
|
|
* All rights reserved.</center></h2>
|
||
|
|
*
|
||
|
|
* This software component is licensed by ST under Ultimate Liberty license
|
||
|
|
* SLA0044, the "License"; You may not use this file except in compliance with
|
||
|
|
* the License. You may obtain a copy of the License at:
|
||
|
|
* www.st.com/SLA0044
|
||
|
|
*
|
||
|
|
******************************************************************************
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Includes ------------------------------------------------------------------*/
|
||
|
|
#include "tim.h"
|
||
|
|
|
||
|
|
/* USER CODE BEGIN 0 */
|
||
|
|
|
||
|
|
/* USER CODE END 0 */
|
||
|
|
|
||
|
|
TIM_HandleTypeDef htim2;
|
||
|
|
TIM_HandleTypeDef htim3;
|
||
|
|
TIM_HandleTypeDef htim5;
|
||
|
|
DMA_HandleTypeDef hdma_tim5_ch2;
|
||
|
|
|
||
|
|
/* TIM2 init function */
|
||
|
|
void MX_TIM2_Init(void)
|
||
|
|
{
|
||
|
|
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
|
||
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
||
|
|
TIM_OC_InitTypeDef sConfigOC = {0};
|
||
|
|
|
||
|
|
htim2.Instance = TIM2;
|
||
|
|
htim2.Init.Prescaler = 107;
|
||
|
|
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
|
||
|
|
htim2.Init.Period = 20000;
|
||
|
|
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
||
|
|
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
||
|
|
if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
|
||
|
|
{
|
||
|
|
Error_Handler();
|
||
|
|
}
|
||
|
|
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
|
||
|
|
if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
|
||
|
|
{
|
||
|
|
Error_Handler();
|
||
|
|
}
|
||
|
|
if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
|
||
|
|
{
|
||
|
|
Error_Handler();
|
||
|
|
}
|
||
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
||
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
||
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
|
||
|
|
{
|
||
|
|
Error_Handler();
|
||
|
|
}
|
||
|
|
sConfigOC.OCMode = TIM_OCMODE_PWM1;
|
||
|
|
sConfigOC.Pulse = 0;
|
||
|
|
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
|
||
|
|
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
|
||
|
|
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
|
||
|
|
{
|
||
|
|
Error_Handler();
|
||
|
|
}
|
||
|
|
HAL_TIM_MspPostInit(&htim2);
|
||
|
|
|
||
|
|
}
|
||
|
|
/* TIM3 init function */
|
||
|
|
void MX_TIM3_Init(void)
|
||
|
|
{
|
||
|
|
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
|
||
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
||
|
|
TIM_OC_InitTypeDef sConfigOC = {0};
|
||
|
|
|
||
|
|
htim3.Instance = TIM3;
|
||
|
|
htim3.Init.Prescaler = 107;
|
||
|
|
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
|
||
|
|
htim3.Init.Period = 499;
|
||
|
|
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
||
|
|
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
||
|
|
if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
|
||
|
|
{
|
||
|
|
Error_Handler();
|
||
|
|
}
|
||
|
|
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
|
||
|
|
if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
|
||
|
|
{
|
||
|
|
Error_Handler();
|
||
|
|
}
|
||
|
|
if (HAL_TIM_OC_Init(&htim3) != HAL_OK)
|
||
|
|
{
|
||
|
|
Error_Handler();
|
||
|
|
}
|
||
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
||
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
||
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
|
||
|
|
{
|
||
|
|
Error_Handler();
|
||
|
|
}
|
||
|
|
sConfigOC.OCMode = TIM_OCMODE_TIMING;
|
||
|
|
sConfigOC.Pulse = 0;
|
||
|
|
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
|
||
|
|
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
|
||
|
|
if (HAL_TIM_OC_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
|
||
|
|
{
|
||
|
|
Error_Handler();
|
||
|
|
}
|
||
|
|
|
||
|
|
}
|
||
|
|
/* TIM5 init function */
|
||
|
|
void MX_TIM5_Init(void)
|
||
|
|
{
|
||
|
|
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
|
||
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
||
|
|
TIM_OC_InitTypeDef sConfigOC = {0};
|
||
|
|
|
||
|
|
htim5.Instance = TIM5;
|
||
|
|
htim5.Init.Prescaler = 8;
|
||
|
|
htim5.Init.CounterMode = TIM_COUNTERMODE_UP;
|
||
|
|
htim5.Init.Period = 19;
|
||
|
|
htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
||
|
|
htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
||
|
|
if (HAL_TIM_Base_Init(&htim5) != HAL_OK)
|
||
|
|
{
|
||
|
|
Error_Handler();
|
||
|
|
}
|
||
|
|
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
|
||
|
|
if (HAL_TIM_ConfigClockSource(&htim5, &sClockSourceConfig) != HAL_OK)
|
||
|
|
{
|
||
|
|
Error_Handler();
|
||
|
|
}
|
||
|
|
if (HAL_TIM_PWM_Init(&htim5) != HAL_OK)
|
||
|
|
{
|
||
|
|
Error_Handler();
|
||
|
|
}
|
||
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
||
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
||
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK)
|
||
|
|
{
|
||
|
|
Error_Handler();
|
||
|
|
}
|
||
|
|
sConfigOC.OCMode = TIM_OCMODE_PWM1;
|
||
|
|
sConfigOC.Pulse = 0;
|
||
|
|
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
|
||
|
|
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
|
||
|
|
if (HAL_TIM_PWM_ConfigChannel(&htim5, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
|
||
|
|
{
|
||
|
|
Error_Handler();
|
||
|
|
}
|
||
|
|
HAL_TIM_MspPostInit(&htim5);
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
|
||
|
|
{
|
||
|
|
|
||
|
|
if(tim_baseHandle->Instance==TIM2)
|
||
|
|
{
|
||
|
|
/* USER CODE BEGIN TIM2_MspInit 0 */
|
||
|
|
|
||
|
|
/* USER CODE END TIM2_MspInit 0 */
|
||
|
|
/* TIM2 clock enable */
|
||
|
|
__HAL_RCC_TIM2_CLK_ENABLE();
|
||
|
|
/* USER CODE BEGIN TIM2_MspInit 1 */
|
||
|
|
|
||
|
|
/* USER CODE END TIM2_MspInit 1 */
|
||
|
|
}
|
||
|
|
else if(tim_baseHandle->Instance==TIM3)
|
||
|
|
{
|
||
|
|
/* USER CODE BEGIN TIM3_MspInit 0 */
|
||
|
|
|
||
|
|
/* USER CODE END TIM3_MspInit 0 */
|
||
|
|
/* TIM3 clock enable */
|
||
|
|
__HAL_RCC_TIM3_CLK_ENABLE();
|
||
|
|
|
||
|
|
/* TIM3 interrupt Init */
|
||
|
|
HAL_NVIC_SetPriority(TIM3_IRQn, 5, 0);
|
||
|
|
HAL_NVIC_EnableIRQ(TIM3_IRQn);
|
||
|
|
/* USER CODE BEGIN TIM3_MspInit 1 */
|
||
|
|
|
||
|
|
/* USER CODE END TIM3_MspInit 1 */
|
||
|
|
}
|
||
|
|
else if(tim_baseHandle->Instance==TIM5)
|
||
|
|
{
|
||
|
|
/* USER CODE BEGIN TIM5_MspInit 0 */
|
||
|
|
|
||
|
|
/* USER CODE END TIM5_MspInit 0 */
|
||
|
|
/* TIM5 clock enable */
|
||
|
|
__HAL_RCC_TIM5_CLK_ENABLE();
|
||
|
|
|
||
|
|
/* TIM5 DMA Init */
|
||
|
|
/* TIM5_CH2 Init */
|
||
|
|
hdma_tim5_ch2.Instance = DMA1_Stream4;
|
||
|
|
hdma_tim5_ch2.Init.Channel = DMA_CHANNEL_6;
|
||
|
|
hdma_tim5_ch2.Init.Direction = DMA_MEMORY_TO_PERIPH;
|
||
|
|
hdma_tim5_ch2.Init.PeriphInc = DMA_PINC_DISABLE;
|
||
|
|
hdma_tim5_ch2.Init.MemInc = DMA_MINC_ENABLE;
|
||
|
|
hdma_tim5_ch2.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
|
||
|
|
hdma_tim5_ch2.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
|
||
|
|
hdma_tim5_ch2.Init.Mode = DMA_NORMAL;
|
||
|
|
hdma_tim5_ch2.Init.Priority = DMA_PRIORITY_VERY_HIGH;
|
||
|
|
hdma_tim5_ch2.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
|
||
|
|
hdma_tim5_ch2.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_1QUARTERFULL;
|
||
|
|
hdma_tim5_ch2.Init.MemBurst = DMA_MBURST_SINGLE;
|
||
|
|
hdma_tim5_ch2.Init.PeriphBurst = DMA_PBURST_SINGLE;
|
||
|
|
if (HAL_DMA_Init(&hdma_tim5_ch2) != HAL_OK)
|
||
|
|
{
|
||
|
|
Error_Handler();
|
||
|
|
}
|
||
|
|
|
||
|
|
__HAL_LINKDMA(tim_baseHandle,hdma[TIM_DMA_ID_CC2],hdma_tim5_ch2);
|
||
|
|
|
||
|
|
/* USER CODE BEGIN TIM5_MspInit 1 */
|
||
|
|
|
||
|
|
/* USER CODE END TIM5_MspInit 1 */
|
||
|
|
}
|
||
|
|
}
|
||
|
|
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle)
|
||
|
|
{
|
||
|
|
|
||
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||
|
|
if(timHandle->Instance==TIM2)
|
||
|
|
{
|
||
|
|
/* USER CODE BEGIN TIM2_MspPostInit 0 */
|
||
|
|
|
||
|
|
/* USER CODE END TIM2_MspPostInit 0 */
|
||
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||
|
|
/**TIM2 GPIO Configuration
|
||
|
|
PA0/WKUP ------> TIM2_CH1
|
||
|
|
*/
|
||
|
|
GPIO_InitStruct.Pin = GPIO_PIN_0;
|
||
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
||
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||
|
|
GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
|
||
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||
|
|
|
||
|
|
/* USER CODE BEGIN TIM2_MspPostInit 1 */
|
||
|
|
|
||
|
|
/* USER CODE END TIM2_MspPostInit 1 */
|
||
|
|
}
|
||
|
|
else if(timHandle->Instance==TIM5)
|
||
|
|
{
|
||
|
|
/* USER CODE BEGIN TIM5_MspPostInit 0 */
|
||
|
|
|
||
|
|
/* USER CODE END TIM5_MspPostInit 0 */
|
||
|
|
|
||
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||
|
|
/**TIM5 GPIO Configuration
|
||
|
|
PA1 ------> TIM5_CH2
|
||
|
|
*/
|
||
|
|
GPIO_InitStruct.Pin = GPIO_PIN_1;
|
||
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||
|
|
GPIO_InitStruct.Alternate = GPIO_AF2_TIM5;
|
||
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||
|
|
|
||
|
|
/* USER CODE BEGIN TIM5_MspPostInit 1 */
|
||
|
|
|
||
|
|
/* USER CODE END TIM5_MspPostInit 1 */
|
||
|
|
}
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle)
|
||
|
|
{
|
||
|
|
|
||
|
|
if(tim_baseHandle->Instance==TIM2)
|
||
|
|
{
|
||
|
|
/* USER CODE BEGIN TIM2_MspDeInit 0 */
|
||
|
|
|
||
|
|
/* USER CODE END TIM2_MspDeInit 0 */
|
||
|
|
/* Peripheral clock disable */
|
||
|
|
__HAL_RCC_TIM2_CLK_DISABLE();
|
||
|
|
/* USER CODE BEGIN TIM2_MspDeInit 1 */
|
||
|
|
|
||
|
|
/* USER CODE END TIM2_MspDeInit 1 */
|
||
|
|
}
|
||
|
|
else if(tim_baseHandle->Instance==TIM3)
|
||
|
|
{
|
||
|
|
/* USER CODE BEGIN TIM3_MspDeInit 0 */
|
||
|
|
|
||
|
|
/* USER CODE END TIM3_MspDeInit 0 */
|
||
|
|
/* Peripheral clock disable */
|
||
|
|
__HAL_RCC_TIM3_CLK_DISABLE();
|
||
|
|
|
||
|
|
/* TIM3 interrupt Deinit */
|
||
|
|
HAL_NVIC_DisableIRQ(TIM3_IRQn);
|
||
|
|
/* USER CODE BEGIN TIM3_MspDeInit 1 */
|
||
|
|
|
||
|
|
/* USER CODE END TIM3_MspDeInit 1 */
|
||
|
|
}
|
||
|
|
else if(tim_baseHandle->Instance==TIM5)
|
||
|
|
{
|
||
|
|
/* USER CODE BEGIN TIM5_MspDeInit 0 */
|
||
|
|
|
||
|
|
/* USER CODE END TIM5_MspDeInit 0 */
|
||
|
|
/* Peripheral clock disable */
|
||
|
|
__HAL_RCC_TIM5_CLK_DISABLE();
|
||
|
|
|
||
|
|
/* TIM5 DMA DeInit */
|
||
|
|
HAL_DMA_DeInit(tim_baseHandle->hdma[TIM_DMA_ID_CC2]);
|
||
|
|
/* USER CODE BEGIN TIM5_MspDeInit 1 */
|
||
|
|
|
||
|
|
/* USER CODE END TIM5_MspDeInit 1 */
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* USER CODE BEGIN 1 */
|
||
|
|
|
||
|
|
/* USER CODE END 1 */
|
||
|
|
|
||
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|