*

CPU0801.circ

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+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project source="3.9.0" version="1.0">
+  This file is intended to be loaded by Logisim-evolution v3.9.0(https://github.com/logisim-evolution/).
+
+  <lib desc="#Wiring" name="0">
+    <tool name="Pin">
+      <a name="appearance" val="classic"/>
+    </tool>
+  </lib>
+  <lib desc="#Gates" name="1"/>
+  <lib desc="#Plexers" name="2"/>
+  <lib desc="#Arithmetic" name="3"/>
+  <lib desc="#Memory" name="4"/>
+  <lib desc="#I/O" name="5"/>
+  <lib desc="#TTL" name="6"/>
+  <lib desc="#TCL" name="7"/>
+  <lib desc="#Base" name="8"/>
+  <lib desc="#BFH-Praktika" name="9"/>
+  <lib desc="#Input/Output-Extra" name="10"/>
+  <lib desc="#Soc" name="11"/>
+  <main name="main"/>
+  <options>
+    <a name="gateUndefined" val="ignore"/>
+    <a name="simlimit" val="1000"/>
+    <a name="simrand" val="0"/>
+  </options>
+  <mappings>
+    <tool lib="8" map="Button2" name="Poke Tool"/>
+    <tool lib="8" map="Button3" name="Menu Tool"/>
+    <tool lib="8" map="Ctrl Button1" name="Menu Tool"/>
+  </mappings>
+  <toolbar>
+    <tool lib="8" name="Poke Tool"/>
+    <tool lib="8" name="Edit Tool"/>
+    <tool lib="8" name="Wiring Tool"/>
+    <tool lib="8" name="Text Tool"/>
+    <sep/>
+    <tool lib="0" name="Pin"/>
+    <tool lib="0" name="Pin">
+      <a name="facing" val="west"/>
+      <a name="output" val="true"/>
+    </tool>
+    <sep/>
+    <tool lib="1" name="NOT Gate"/>
+    <tool lib="1" name="AND Gate"/>
+    <tool lib="1" name="OR Gate"/>
+    <tool lib="1" name="XOR Gate"/>
+    <tool lib="1" name="NAND Gate"/>
+    <tool lib="1" name="NOR Gate"/>
+    <sep/>
+    <tool lib="4" name="D Flip-Flop"/>
+    <tool lib="4" name="Register"/>
+  </toolbar>
+  <circuit name="main">
+    <a name="appearance" val="logisim_evolution"/>
+    <a name="circuit" val="main"/>
+    <a name="circuitnamedboxfixedsize" val="true"/>
+    <a name="simulationFrequency" val="1.0"/>
+    <comp lib="0" loc="(220,530)" name="Clock">
+      <a name="label" val="CLK"/>
+    </comp>
+    <comp lib="4" loc="(630,460)" name="Register">
+      <a name="appearance" val="logisim_evolution"/>
+      <a name="label" val="REG_A"/>
+      <a name="showInTab" val="true"/>
+      <a name="width" val="16"/>
+    </comp>
+    <comp lib="4" loc="(760,460)" name="Register">
+      <a name="appearance" val="logisim_evolution"/>
+      <a name="label" val="REG_B"/>
+      <a name="showInTab" val="true"/>
+      <a name="width" val="16"/>
+    </comp>
+    <comp lib="4" loc="(890,460)" name="Register">
+      <a name="appearance" val="logisim_evolution"/>
+      <a name="label" val="REG_C"/>
+      <a name="showInTab" val="true"/>
+      <a name="width" val="16"/>
+    </comp>
+    <wire from="(220,530)" to="(290,530)"/>
+  </circuit>
+</project>

Doc/LogicICs/README.md

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+## Basc gates
+* [74LS00](74LS00.pdf) - Quad 2-input positive-NAND gates []
+* [74LS02](74LS02.pdf) - Quad 2-input positive-NOR gates
+* [74LS04](74LS04.pdf) - 6 inverters
+* [74LS08](74LS08.pdf) - Quad 2-Input AND Gates
+* [74LS15](74LS15.pdf) - TRIPLE 3-INPUT POSITIVE-AND GATES WITH OPEN-COLLECTOR OUTPUTS
+* [74LS32](74LS32.pdf) - Quad 2-input positive-OR gates
+* [74LS86](74LS86.pdf) - Quad 2-input XOR gates
+
+## Latches
+74LS107 -  Dual Negative-EdgeTriggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
+74LS273 - OCTAL D-TYPE FLIP-FLOP WITH CLEAR
+74HC573 - Octal D-type transparent latch; 3-state
+
+## Registers
+74LS173 - 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS
+
+## RAM
+74F189 - 64-bit TTL bipolar RAM, inverting (3-State)
+
+## Transcievers
+74HC245 - OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
+
+## Shift registers
+74HC595 - 8-bit serial-in, serial or parallel-outshift register with output latches; 3-state
+
+## Demultiplexers
+74LS138 - 3 line to 8 line demultiplexer
+74LS139 - 2 line to 4 line demultiplexer
+
+## Counters
+74LS161 - 4-BIT BINARY COUNTER
+
+## ALU
+74LS181 - ALU
+
+## Adders
+74LS283 - 4-bit binary full adder with fast carry